SPI communication with additional MISO | LabJack
 

SPI communication with additional MISO

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mina
Synapticon's picture
SPI communication with additional MISO

Hi, I am using the AD7265BCPZ from Analog Devices as ADC. This device is configured for SPI protocol with one CS, one CLK, and 2x MISO. Is it possible to drive such ADC through your SPI communication registers?

I know how to make SPI work on the default IO ports. So could I configure an additional register as MISO that would work with the same CS and CLK. Or configure the additional 3 ports that would share (have the same) CS and CLK?

 

LabJack Support
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I see that the AD7265 has two

I see that the AD7265 has two data outputs. The SPI feature is not set up to handle that. We could easily read from one and then the other, but half the data will always being lost. The only way I can think of to get both data sets is to create a Lua script that will bit-bang the SPI operations and save data from both MISO lines. I think a Lua script will be able run at 5-10 kHz.

mina
Synapticon's picture
Hi, so the bit-banging

Hi, so the bit-banging implementation would be at the cost of significantly reduced clock at 5-10kHz instead of the ~800kHz possible now. Do i understand that correctly?

LabJack Support
labjack support's picture
That's right. Also, the T7's

That's right. Also, the T7's processor will be running the Lua VM. If you want to perform operations in addition to SPI they may run slower.