UART - setting and reading ASYNCH_TX_DIO shows incorrect value

3 posts / 0 new

Tue, 01/21/2020 - 23:16

Mudzin

I’m having a problem setting ASYNCH_TX_DIONUM register on LabJack T7 in Python.

self.rx = 7
self.tx = 6
ljm.eWriteName(self.handle, "ASYNCH_TX_DIONUM", self.tx)
ljm.eWriteName(self.handle, "ASYNCH_RX_DIONUM", self.rx)

Operation ends without error, however, pytest reports error.

assert labjack.read("ASYNCH_RX_DIONUM") == 7
>      assert labjack.read("ASYNCH_TX_DIONUM") == 6
E      assert 7.0 == 6
E      -7.0
E      +6

I’ve run out of ideas… Could please provide any hints? method labjack.read() gets register data by implementing ljm.eReadName(handle, register_name).

Wed, 01/22/2020 - 15:09

LabJack Support

It looks like the TX line is

It looks like the TX line is not readable, and not throwing an error. The value is latched in as expected, just can't be read out. We will look into getting that fixed.

In the meantime UART can still be used. I have attached a lua script which uses a loopback test to transmit and recieve data. Tested with firwmare 1.0287. Be sure to set the RX and TX lines as desired. I was using FIO3 and FIO2.

File Attachment:

UART_Test.lua

Wed, 01/22/2020 - 23:36

Mudzin

Hi. It seems so as you've

Hi. It seems so as you've written. My comm works fine, but readout is wrong. Here's pytest log:

[DEBUG] 2020-01-23 07:32:39,821 :: UART - Configuration Rx: FIO0, Tx: FIO1, Baudrate: 9600, Buffer: 1500, Parity: 0, Stop bits: 1
[DEBUG] 2020-01-23 07:32:39,822 :: UART - Sending data @ FIO1: "HelloWorld!!!!" (14 bytes)
[DEBUG] 2020-01-23 07:32:39,841 :: UART - Reading buffer @ FIO0: ASYNCH_NUM_BYTES_RX=14
[DEBUG] 2020-01-23 07:32:39,848 :: UART - Received data @ FIO0: "HelloWorld!!!!"
[DEBUG] 2020-01-23 07:32:39,849 :: ASYNCH_RX_DIONUM: 0.0
[DEBUG] 2020-01-23 07:32:39,850 :: ASYNCH_TX_DIONUM: 0.0